Graphene is the hexagonal arrangement of carbon atoms forming a one-atom thick planar sheet of sp2 hybridized (double bonded) carbon atoms arranged in a honeycomb lattice. Graphene is a promising electronic material. It has the potential to significantly impact the semiconductor industry due to its superior electrical, thermal, mechanical, and optical properties while at the same time offering compatibility with existing semiconductor processing techniques. Graphene has shown extraordinary applications, including single molecule detection, ultrafast FETs, hydrogen visualization-template for TEM, and tunable spintronic devices. Furthermore, it exhibits high thermal conductivity (25× silicon), high mechanical strength (strongest nanomaterial), high optical transparency (80%), carrier controlled interband/optical-transition and flexible structure. Electronically, graphene is a semi-metal with zero band-gap owing to the conduction band touching the valence band at two points (K and K′) in the Brillouin zone. Graphene's high density of π-electrons from the sp2 carbon atoms and carrier-confinement in an open crystallographic structure imparts it with the highest mobility measured to date.
In order to realize these benefits in volume manufacturing, paths to integrating graphene on large diameter semiconductor, e.g., silicon, substrates are necessary. Current processes require graphene to be transferred from a metal base to the desired substrate. This transfer process of an atomically-thick sheet is challenging and leads to low yield and a significant density of folds and tears.
Since the successful isolation, identification, and characterization of graphene by A. Geim and K. Novoselov in 2004, the most common method for producing flakes of graphene has been by tape exfoliation from graphite and transfer to oxidized silicon wafer. The transfer process for graphene from a metal (a) is not feasible for large scale synthesis due to inconsistent coverage, (b) leaves transfer polymers' residue on graphene (PMMA, PDMS, thermal-adhesive-tape) increasing carrier-scattering, and (c) produces folds, wrinkles and tears. Therefore, transfer of graphene is not feasible for industrial processing. Clearly, the scotch-tape method is not scalable for semiconductor industry. As a result of these deficiencies, this method produces small, irregularly shaped flakes of graphene and is not suitable for scaling to large diameter integration with silicon. See A. K. Geim and K. S. Novovselov, “The Rise of Graphene” Nature Materials 6 (2007) 183-191.
Research into producing wafer level graphene and large area sheets of graphene has produced the development of two main options.
First, W. deHeer's group at Georgia Institute of Technology has demonstrated the formation of graphene layers on SiC wafer by silicon sublimation and outdiffusion at very high temperature. The disadvantage of this technique is the high cost of SiC wafers, the smaller diameter SiC wafers, and the absence of integration scale possible on silicon wafers. Some groups are working on depositing SiC on Silicon and attempting to form graphene on the deposited SiC layer. See P. First, W. deHeer et al, “Epitaxial Graphenes on Silicon Carbide” MRS Bulletin 35, 296-305 (2010).
Groups in Korea and the University of Texas system have demonstrated graphene formation on metal foils such as Cu and Ni. See S. Bae et al, “Roll-to Roll Production of 30 inch Graphene Films for Transparent Electrodes” Nature Nanotechnology 5, 574-578 (2010) and X. Li et al, ECS Transactions, “Synthesis, Characterization, and Properties of Large-Area Graphene Films” 19 (5), 41-52 (2005). Using a carbon source such as methane mixed with hydrogen at temperatures in the 700-1000° C. range in a CVD chamber at pressure such as 500 mtorr, carbon is absorbed into the metal film and upon cooling segregates or precipitates to the surface of the metal foil forming single or multi-layer graphene depending on the process conditions and the metal foil. The graphene layer then has to be transferred to oxidized silicon. The transfer process generally uses a material like PMMA on graphene followed by dissolution of the metal foil, then graphene is interfaced to the silicon dioxide layer, and finally the PMMA is removed leaving graphene on SiO2 on Silicon. Although the graphene formation on metal foils enables large sheets of graphene to be produced, the process for transferring large area graphene sheets to large diameter silicon substrates for electronic device fabrication is challenging. Issues such as film stress, chemical residues, bonding defects, and wrinkles in the graphene film are likely to be significant challenges for a manufacturable process.